Memory arrays are utilized for tightly packing memory cells within integrated circuitry. One type of memory which is particularly amenable to tight packing is cross-point memory.
A memory array may comprise a plurality of wordlines extending along a first direction, and a plurality of bitlines extending orthogonally to the wordlines. Cross-point memory may utilize memory cell material formed at the intersections of the bitlines and wordlines across the array. The memory cell material may be phase change material, such as chalcogenides. Example chalcogenides are alloys of germanium, antimony and tellurium.
In addition to the memory cell material, the individual memory cells may also comprise access devices which limit current to the memory cell material until a voltage differential across the memory cell material and the access device reaches a predetermined threshold. The access devices may be non-linear electronic devices. Specifically, the access devices may be electronic devices which are in a highly resistive state until a voltage differential reaches a predetermined value, whereupon the electronic devices transform to a conducting state. Example access devices are diodes and ovonic threshold switches.
An example prior art cross-point memory array 5 is shown in FIGS. 1-3; with FIG. 1 being a top view, and with FIGS. 2 and 3 being cross-sectional side views. The cross-sectional views of FIGS. 2 and 3, like all other cross-sectional views in this disclosure, only show features within the planes of the cross-sections. The cross-sectional views do not show materials behind the planes of the cross-sections in order to simplify the drawings.
The top view of FIG. 1 shows that the memory array comprises a plurality of global bitlines 10-14 that extend along a first horizontal direction, and comprises a plurality of wordlines 20-25 that extend orthogonally to the global bitlines. The cross-sectional side view of FIG. 2 shows that the wordlines of FIG. 1 are actually the top series of a stack of wordlines, with FIG. 2 showing two underlying series of wordlines. The wordlines within one of the underlying series are labeled as wordlines 20a-25a, and the wordlines in the other of the underlying series are labeled as wordlines 20b-25b. 
Eighteen wordlines (20-25, 20a-25a and 20b-25b) are shown in the cross-sectional view of FIG. 2. The eighteen wordlines form a two-dimensional wordline array having columns of three wordlines, and rows of six wordlines.
FIGS. 1-3 show that vertical bitline pillars 30-44 extend upwardly from the global bitlines. The bitline pillars extend through the wordline array, and are between some of the columns of such wordline array. The wordlines, bitlines and vertical bitline pillars comprise electrically conductive material, such as, for example, one or more of various metals, metal-containing compositions, and conductively-doped semiconductor materials.
Memory cell material 45 (only some of which is labeled) is provided between the wordlines and vertical bitline pillars; and access devices 46 (only some of which are labeled) are provided between the wordlines and the vertical bitline pillars. The memory cell material and access device provided between a wordline and a vertical bitline pillar together form a memory cell 47 (only some of which are labeled).
Although the memory cell material is shown to be a single homogeneous composition, it may comprise multiple discrete compositions in some applications. Also, although the access devices are shown to comprise single, homogeneous compositions, the access devices may comprise numerous discrete compositions; and often do comprise two or more different materials. Further, although only a single access device is shown in each memory cell, there can be multiple access devices in the individual memory cells. Also, although the memory cell material is shown directly adjacent the vertical bitline pillars, and the access devices are shown directly adjacent the wordlines, the relative orientations of the memory cell material and the access devices may be reversed.
In operation, each individual memory cell may be uniquely addressed by a combination of a global bitline and a wordline. For instance, a voltage differential between global bitline 12 and wordline 20 may be utilized to access the memory cell located at the intersection where wordline 20 crosses vertical bitline pillar 36. Such access may be utilized for writing to the memory cell by placing the memory cell in a specific data storage state, and for reading from the memory cell by ascertaining which data storage state the memory cell is in.
The wordlines within the two-dimensional wordline array of FIG. 2 may be considered to be arranged in a plurality of elevational planes 50-52, and accordingly the top view of FIG. 1 may be considered to be showing the uppermost elevational plane 52 of the wordline array. The memory array may be considered to also comprise the elevational planes 50-52, and each memory unit of the memory array may be considered to have an area along the elevational plane containing such memory unit. The area may be stated in terms of a minimum feature size, F, utilized to form the memory array. Such minimum feature size will be the widths of the bitlines, the widths of the wordlines, the widths of the vertical bitline pillars, and the widths of the spaces between the bitlines and the wordlines if the memory array is fabricated to its absolute minimum dimensions.
The top view of FIG. 1 shows a square perimeter around one of the memory units. Such perimeter has sides that are of dimension 2 F, and accordingly the memory unit has an area along elevational plane 52 of about 4 F2. The area is referred to as being “about 4 F2,” rather than as being absolutely 4 F2 because the illustrated perimeter assumes that the memory cell material 45 and access device 46 are of negligible size. Since the memory cell material 45 and access device 46 have some physical dimension, the planar area of the memory unit cell will approach 4 F2, but will not be 4 F2 in an absolute mathematical sense. Alternatively, the planar area of each memory cell unit may be considered to be 4 F2 in a context in which the memory cell material and access device are ignored; or in other words may be considered to be 4 F2 relative to the wordlines, bitlines and spaces consumed by each memory cell unit.